The invention relates generally to semiconductor device fabrication and, in particular, to methods for fabricating a metal-insulator-metal (MIM) capacitor and structures for a MIM capacitor.
On-chip passive elements, such as MIM capacitors, are deployed in many types of integrated circuits, such as radiofrequency integrated circuits (RFICs), and may be integrated into one or more of the metallization levels of the BEOL interconnect structure using the BEOL metallurgy. The BEOL interconnect structure is routinely fabricated by damascene processes. For example, in a dual damascene process, vias and trenches are etched in one or more dielectric layers using reactive ion etching (RIE) and are simultaneously filled with a plugs and wiring using a single blanket deposition of a conductor and planarization. The process of dielectric deposition, via and trench etch, conductor deposition, and planarization is replicated to generate stacked metallization levels of the BEOL interconnect structure.
A MIM capacitor is a stacked structure formed in the BEOL interconnect structure. A two-electrode MIM capacitor includes planar top and bottom conductive plates, which operate as electrodes, and an interplate dielectric layer disposed between the top and bottom conductive plates as an electrical insulator. The capacitance, or amount of charge held by the MIM capacitor per applied voltage, depends upon the area of the top and bottom conductive plates, their separation, and the dielectric constant of the material constituting the interplate dielectric layer.
Improved methods are needed for fabricating MIM capacitors, as well as improved structures for MIM capacitors.